Dynamic Random Access Memory chips (DRAMs) are widely used among semiconductor memory devices because of their high density and low cost. The basic operation of a DRAM is to record data by storing bits as the presence ("1") or absence ("0") of electrical charge in memory cell capacitors. Silicon oxide film is often used as the dielectric film of the memory cell capacitor of the DRAM, but if the memory data is to be nonvolatile, ferroelectric film may be used instead.
A conventional DRAM using ferroelectric capacitors as taught by prior art is represented in the circuit diagram of FIG. 5. In each cell 30, a pair of bit lines, 35 and 36, or 37 and 38, are connected by MOS transistors 31, 31' to memory cell capacitors 33, 33' as well as to sense amplifiers 41, 42.
The MOS transistors 31, 31' are controlled by a connected word line 32, 34, and memory cell capacitors 33, 33' are connected to cell plate electrodes 39, 40. A control signal .phi.P controls MOS transistors 43, 44, 45, 46, either grounding or precharging bit lines 35, 36, 37, 38. A second control signal .phi.S controls sense amplifiers 41, 42.
In the illustrative example, each memory cell 30 has two memory cell capacitors 33, 33' and two MOS transistors 31, 31'. Data is stored by writing a logical voltage (data value "0" or "1") into a memory cell by storing that value in one of the memory cell capacitors and the opposite value ("1" or "0") in the other memory cell capacitor. This stored data can then be read by connecting the memory cell capacitors to the bit lines and amplifying the voltage difference with the sense amplifier 41, 42.
When the memory cell capacitor is connected to the bit line to read the data, if the value stored was a "0," the memory cell capacitor is not holding any charge and its state is not affected by the read. However, if the value was a "1," the memory cell capacitor charge indicating a voltage is dissipated when the value is read onto the bit line and must be rewritten if the data is to be retained.
Moreover, even if not destroyed by read-outs, because the data is stored in a capacitor, the charge will gradually dissipate. To minimize the chance that a "1" will be mistakenly read as a "0," the bit lines onto which the data are read are connected to sense amplifiers to detect the presence of even slight charges. Eventually however, the stored charge will decrease to a level which may not be detected even by the sense amplifier.
The operation of the prior art memory device of FIG. 5 can be explained in greater detail with reference to FIGS. 6 and 7. FIG. 6 shows a hysteresis curve of the memory cell; FIG. 7 is a timing chart of the operations of memory cell 30a.
As shown in FIG. 7, initially, word line 32, cell plate electrode 39, bit lines 35, 36 and control signal .phi.S are all at a low logical voltage "L," while control signal .phi.P is at a high logical voltage "H." To enable the memory device to read the data stored in memory cell capacitors 33a, 33a', control signal .phi.P is changed to "L" and bit lines 35, 36 are shifted to a floating state. Word line 32 and cell plate electrode 39 are then changed to "H," turning on MOS transistors 31a, 31a' and enabling the data stored in memory cell capacitors 33a, 33a' to be read respectively onto the bit lines 35, 36.
The potential difference between the charges read out from memory cell capacitors 33a, 33a' onto bit lines 35, 36 is shown in the hysteresis curve of FIG. 6. After data is stored in a ferroelectric capacitor and the power supply is cut off, the electric field is zero and the residual polarizations in the ferroelectric capacitor are utilized as nonvolatile data. The residual polarization for high and low voltages are represented respectively by points B and E: When the data value stored in a memory cell is a "1," one of the two memory cell capacitors stands at point B and the other stands at point E. When the data value stored in a memory cell is a "0," the situation is reversed, with the first of the memory cell capacitors at point E and the other at point B.
Still referring to FIG. 6, the slope of straight lines L1, L2 depends on the parasitic capacitance of the bit lines 35, 36: the less parasitic the capacitance, the smaller the absolute value of the slope. Lines L1, L2 are further defined by points M21 and N21, which are shifted horizontally from points B and E respectively, by a magnitude of electric field produced when the voltages of word line 32 and cell plate electrode 39 shift from "L" to "H."
The curves from the points B and E to point D represent the electrical charge held in memory cell capacitors 33a, 33a' as the electrical field changes due to the voltage shift of word line 32 and cell plate electrode 39 from "L" to "H." When a stored data value "1" is read out on bit line 35 from memory cell capacitor 33a, the state of the memory cell capacitor 33a moves from point B to point 021, where the hysteresis curve intersects with line L1 Similarly, the state of memory cell capacitor 33a', which carries an opposite logic value from memory cell capacitor 33a, moves from point E to point P21, where the hysteresis curve intersects with line L2. Thus the read-out potential difference between the pair of bit lines 35, 36 becomes Vr21, the difference of the electric fields between point 021 and point P21.
To read out the data on bit lines 35, 36, the potential difference Vr21 is amplified and control signal .phi.S is shifted from "L" to "H." When the amplification in the sense amplifier 41 is complete, the state of bit line 35 shifts from point 021 to point Q21, and the state of bit line 36 shifts from point P21 to point D.
When the data is read, the charges in the memory cell capacitors 33a, 33a' dissipate and must be rewritten. Voltage at cell plate electrode 39 shifts from "L" to "H," moving bit line 35 from point Q21, to point A, to point B. Similarly, bit line 36 moves from point D to point E. This completes the rewriting process, restoring the semiconductor memory device to its initial state: word line 32 and control signal .phi.S are shifted to "L," control signal .phi.P is shifted to "H," and bit lines 35, 36 are returned to "L" from floating state.
If the value stored in memory cell 30a is "0" rather than "1," with the effect that memory cell capacitor 33a stores a "0" and memory cell capacitor 33a' stores a "1," the states of the bit lines 35, 36 are reversed, but the process remains the same and the potential difference remains Vr21.
In the prior art semiconductor memory device using a dielectric film as described above, every time a memory cell capacitor storing a data value "1" is read, the charge indicating that value is dissipated and must be rewritten. Each rewriting applies stress to the dielectric film of that memory cell capacitor, and the deteriorating effects of repeated stress are particularly severe when ferroelectric film is used, due to the property change when oxygen is emitted by the film: As shown in FIG. 8, repeated writing shrinks the original loop ABDE of the hysteresis curve to the smaller loop abde. As a result, residual electric charges decrease to a level which may result in the stored data being erroneously read.
Accordingly, there exists a need for a semiconductor memory device with an enhanced capability to accurately store data while withstanding multiple read and write operations.